This invention relates to oscillator circuits, for example, a voltage controlled oscillator circuit for a phase-lock-loop.
Phase-locked-loop (PLL) circuits are utilized in many applications to provide an output signal that is substantially the same frequency and phase of an input reference signal. The main components of a PLL circuit comprise a phase/frequency detector, a loop filter, a voltage controlled oscillator (VCO), and an optional divide by N block which is typically implemented with a counter. When in lock, the output signal of the VCO, signal VCO.sub.OUT, is substantially N times the frequency and phase as the input reference signal. The phase/frequency detector typically has two inputs and two outputs. The two inputs include the input reference signal and the divide by N VCO feedback signal, signal VCO.sub.OUT /N, while the two outputs of the phase/frequency detector provide an UP and a DOWN signal. The phase/frequency detector compares the input reference signal to signal VCO.sub.OUT /N and operates such that if the frequency of signal VCO.sub.OUT /N is lower than the frequency of the input reference signal, the UP signal functions to increase the operating frequency of the VCO. Furthermore, if the frequency of signal VCO.sub.OUT /N is at a higher frequency than the input reference signal, the DOWN signal functions to decrease the operating frequency of the VCO. Further, when the phase-locked-loop is in lock, the input reference signal and signal VCO.sub.OUT /N are substantially equal in frequency and phase.
VCO's are designed to operate at a predetermined frequency based upon an applied control voltage wherein an internal 50% duty cycle clock is typically derived from the VCO operating frequency. Further, the 50% duty cycle clock is typically equal to one-half of the operating frequency of the VCO and is generated by passing the output signal of the VCO through a divide by 2 block. Therefore, in order to obtain a 50% duty cycle clock at 40 MHz, the VCO would have to be operating at 80 MHz. However, the frequency and frequency-gain factor of typical VCO's are sensitive to process and temperature variations. As a result, if the frequency-gain factor of the VCO is large, then the VCO typically becomes unstable and sensitive to noise. Further, this could impose a limit on designing high frequency phase-locked loop systems.
Hence, a need exists for a voltage controlled oscillator circuit which directly provides a 50% duty cycle clock.